A liquid crystal display with low-temperature polysilicon thin film transistors (LTPS-TFTs) has merits of high resolution, fast response speed, high luminance, high aperture ratio, etc. Due to the characteristics of LTPS, LTPS-TFTs have high electron mobility. In addition, a peripheral drive circuit can also be produced on a glass substrate of the LCD together with a pixel array, so as to achieve goals of system integration, space saving and cost reduction for a drive IC, and this may decrease yield of products as well.
With the development trend toward miniaturization, an LTPS-TFT has become more and more small gradually. However, because the power supply voltage and the working voltage of the LTPS-TFT are not reduced to a great degree correspondingly, the electric field intensity in operation is increased consequently, which leads to increasing of motion rate of electrons. In this case, when the energy of electrons is high enough, the electrons will leave a substrate and tunnel into a gate oxide layer, which phenomenon is called as a hot carrier effect. This effect will cause the threshold voltage of an N-type metal oxide semiconductor (NMOS) to increase, or the threshold voltage of P-type metal oxide semiconductor (PMOS) to decrease, thus affecting characteristic parameters of a MOS, such as threshold voltage (VT), transconductance (gm), sub-threshold slope (St), saturation current (Idsat), etc. This results in degradation of characteristics of an MOS, and brings about a long-teim reliability problem.
In a fabrication process of a traditional LTPS-TFT array substrate, heavy doping on a polysilicon layer is included, namely, an ion implantation is conducted so as to form source and drain regions (SD). Owing to a higher doping concentration, source and drain regions are very close to a gate electrode, and it will produce a strong electric field in the vicinity of source and drain regions and result in the hot carrier effect. When TFTs are turned off, leakage current (off-state current) is overlarge, so that the performance of TFTs is very unstable.
At present, in order to decrease a leakage current, it is usually required that a light doping process be conducted on the drain region, so as to reduce the leakage current by way of decreasing the electric field at the boundary of the drain electrode. For example, one fabrication method comprises the following steps.
Step S101, as illustrated in FIG. 1, a polysilicon layer is formed on a substrate 10, and then it is formed to be an active layer through one patterning process, and the active layer comprises a channel area 200 and first patterns 201 located on two sides of the channel area, as well as third patterns 203 located on the sides of the first patterns 201 away from the channel area 200.
S102, as illustrated in FIG. 2, a gate insulating layer 30 is formed on the substrate 10, and a first photoresist pattern 401 corresponding to the channel area 200 and the first patterns 201 is formed.
S103, as illustrated in FIG. 3, a first ion implantation process is conducted to form heavily doped regions 2031 at the location of the third patterns 203, and then the first photoresist pattern 401 is removed.
S104, as illustrated in FIG. 4, after completion of the above steps, a gate electrode 50 positioned over the channel area 200 is formed, and a second ion implantation process is conducted, so as to form lightly doped regions 2011 at the location of the first patterns 201.
S105, as illustrated in FIG. 5, on the substrate subjected to the above steps, a protection layer 60, a source electrode 701 and a drain electrode 702, and a pixel electrode 801 electrically connected to the drain electrode 702 are formed.
Although the leakage current can be suppressed to a certain extent by the above method, it still has such problems that the effect is not good enough, the boundary defect is high, and so on.